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ultralow distortion, high speed 0.95 nv/ ? hz voltage noise op amp data sheet ad8099 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2003C2013 analog devices, inc. all rights reserved. technical support www.analog.com features ultralow noise: 0.95 nv/ hz , 2.6 pa/ hz ultralow distortion 2 nd harmonic r l = 1 k , g = +2 ?92 db @ 10 mhz 3 rd harmonic r l = 1 k , g = +2 ?105 db @ 10 mhz high speed gbwp: 3.8 ghz C3 db bandwidth: 700 mhz (g = +2) 550 mhz (g = +10) slew rate: 475 v/s (g = +2) 1350 v/s (g = +10) new pinout custom external compensation, gain range C1, +2 to +10 supply current: 15 ma offset voltage: 0.5 mv max wide supply voltage range: 5 v to 12 v applications pre-amplifiers receivers instrumentation filters if and baseband amplifiers a-to-d drivers dac buffers optical electronics connection diagrams 04511-0-001 disable 1 feedback 2 ?in 3 +in 4 +v s 8 v out 7 c c 6 ?v s 5 notes 1. solder the exposed paddle to the ground plane. 04511-0-002 1 feedback 2 ?in 3 +in ?v s 4 disable 8 +v s 7 v out 6 c c 5 notes 1. solder the exposed paddle to the ground plane. figure 1. 8-lead lfcsp (cp-8-2) fi gure 2. 8-lead soic-ep (rd-8-1) general description the ad8099 is an ultralow noise (0.95 nv/ hz ) and distortion (C92 dbc @10 mhz) voltage feedback op amp, the combination of which make it ideal for 16- and 18-bit systems. the ad8099 features a new, highly linear, low noise input stage that increases the full power bandwidth (fpbw) at low gains with high slew rates. adis proprietary next generation xfcb process enables such high performance amplifiers with relatively low power. the ad8099 features external compensation, which lets the user set the gain bandwidth product. external compensation allows gains from +2 to +10 with minimal trade-off in band- width. the ad8099 also features an extremely high slew rate of 1350 v/s, giving the designer flexibility to use the entire dynamic range without trading off bandwidth or distortion. the ad8099 settles to 0.1% in 18 ns and recovers from overdrive in 50 ns. the ad8099 drives 100 loads at breakthrough performance levels with only 15 ma of supply current. with the wide supply voltage range (5 v to 12 v), low offset voltage (0.1 mv typ), wide bandwidth (700 mhz for g = +2), and a gbwp up to 3.8 ghz, the ad8099 is designed to work in a wide variety of applications. the ad8099 is available in a 3 mm 3 mm lead frame chip scale package (lfcsp) with a new pinout that is specifically optimized for high performance, high speed amplifiers. the new lfcsp package and pinout enable the breakthrough performance that previously was not achievable with amplifiers. the ad8099 is rated to work over the extended industrial temperature range, ?40c to +125c. 04511-a-013 frequency (mhz) 0.1 1.0 10.0 harmonic distortion (dbc) ?130 ?40 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?120 solid line ? second harmonic dotted line ? third harmonic g = +2 v out = 2v p-p v s = 5v r l = 1k ? figure 3. harmonic distortion vs. frequency and gain (soic)
important links for the ad8099 * last content update 08/25/2013 09:10 pm parametric selection tables find similar products by operating parameters high speed amplifiers selection table documentation an-0993: active filter evaluation board for analog devices, inc., - low distortion pinout op amps an-649: using the analog devices active filter design tool an-581: biasing and decoupling op amps in single supply applications an-402: replacing output clamping op amps with input clamping amps an-417: fast rail-to-rail operational amplifiers ease design constraints in low voltage high speed systems mt-101: decoupling techniques mt-059: compensating for the effects of input capacitance on vfb and cfb op amps used in current-to-voltage converters mt-058: effects of feedback capacitance on vfb and cfb op amps mt-056: high speed voltage feedback op amps mt-053: op amp distortion: hd, thd, thd + n, imd, sfdr, mtpr mt-052: op amp noise figure: dont be mislead mt-050: op amp total output noise calculations for second-order system mt-049: op amp total output noise calculations for single-pole system mt-048: op amp noise relationships: 1/f noise, rms noise, and equivalent noise bandwidth mt-047: op amp noise mt-033: voltage feedback op amp gain and bandwidth mt-032: ideal voltage feedback (vfb) op amp a stress-free method for choosing high-speed op amps ug-064: ad8099 evaluation board user guide low-cost video multiplexing using high-speed amplifiers a practical guide to high-speed printed-circuit-board layout op-amp architecture claims better balance of trade-offs evaluation kits & symbols & footprints view the evaluation boards and kits page for documentation and purchasing symbols and footprints design tools, models, drivers & software dbm/dbu/dbv calculator analog filter wizard 2.0 power dissipation vs die temp adisimopamp? opamp stability ad8099 spice macro-model design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy ad8099 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
ad8099 data sheet rev. d | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 connection diagrams ...................................................................... 1 general description ......................................................................... 1 specifications ..................................................................................... 3 specifications with 5 v supply ................................................. 3 specifications with +5 v supply ................................................. 4 absolute maximum ratings ............................................................ 5 maximum power dissipation ..................................................... 5 esd caution .................................................................................. 5 typical performance characteristics ............................................. 6 theory of operation ...................................................................... 15 applications ..................................................................................... 16 using the ad8099 ...................................................................... 16 circuit components .................................................................. 16 recommended values ............................................................... 17 circuit configurations .............................................................. 17 performance vs. component values ........................................ 19 total output noise calculations and design ......................... 20 input bias current and dc offset ........................................... 21 disable pin and input bias cancellation ............................. 21 16- bit adc driver ..................................................................... 22 circuit considerations .............................................................. 23 design tools and technical support ....................................... 23 outline dimensions ....................................................................... 24 ordering guide ............................................................................... 25 revision history 8/13 rev. c to rev . d change s to figure 42 caption ....................................................... 12 change s to figure 4 9 ...................................................................... 13 changes to ordering guide .......................................................... 25 1/13 rev. b to rev . c added epad note to figure 1 and figure 2 ................................. 1 change s to pcb layout section and desig n tools and technical support section ............................................................. 23 deleted figure 72, figure 73, evaluation boards section, and table 7 .............................................................................................. 24 updated outline dimensions ....................................................... 25 changes to ordering guide .......................................................... 26 6 /04 data sheet changed from rev . a to rev . b change to general description ...................................................... 1 chang es to maximum pow er dissipation section ....................... 5 change s to applications section .................................................. 16 changes to table 7 .......................................................................... 24 changes to ordering guide .......................................................... 26 1 /0 4 data sheet changed from rev . 0 to rev . a inserted new figure 3 ................................................................... 1 changes to specifications ............................................................. 3 inserted new figures 22 to 34 ...................................................... 8 inserted new figures 51 to 55 ................................................... 14 changes t o theory of operation section ................................ 16 changes to circuit components section ................................ 17 changes to table 4 ...................................................................... 18 changes to figure 60 .................................................................. 18 changes to total output noise calculations and design section ........................................................................ 21 changes to figure 6 0 .................................................................. 22 changes to figure 62 .................................................................. 23 changes to 16 - bit adc driver section ................................... 23 changes to table 6 ...................................................................... 23 additions to pcb layout section ............................................. 23 11/03 revision 0: initial version
data sheet ad8099 rev. d | page 3 of 28 specifications specifications with 5 v supply t a = 25c, g = +2, r l = 1 k ? to ground , unless otherwise noted. refer to figure 60 through figure 66 for component values and gain configurations . table 1. parameter conditions min typ max unit dynamic perf ormance C 3 db bandwidth g = +5, v out = 0.2 v p -p 450 510 mhz g = +5, v out = 2 v p -p 205 235 mhz bandwidth for 0.1 db flatness (soic/ lf csp) g = +2, v out = 0.2 v p -p 34/25 mhz slew rate g = +10, v out = 6 v step 1120 13 50 v/s g = +2, v out = 2 v step 435 470 v/s settling time to 0.1% g = +2, v out = 2 v step 18 ns noise/distortion performance harmonic distortion (dbc) hd2/hd3 f c = 500 khz, v out = 2 v p - p, g = +10 C 102/ C 11 1 dbc f c = 10 mhz, v out = 2 v p - p, g = +10 C 84/ C92 dbc input voltage noise f = 100 khz 0.95 nv/ hz input current noise f = 100 khz, disable pin floating 2.6 pa/ hz f = 100 khz, disable pin = +v s 5.2 pa/ hz dc performance input offset voltage 0.1 0.5 mv input offset voltage drift 2.3 v/c input bias current disable pin floating C6 C 13 a disable pin = +v s C 0.1 C2 a input bias current drift 3 n a/c input bias offset current 0.06 1 a open - loop gain 82 85 db input characteristics input resistance differential mode 4 k? common mode 10 m? input capacitance 2 pf input common - mode voltage range C 3.7 to +3.7 v common - mode rejection ratio v cm = 2.5 v 98 105 db disable pin disable input voltage output disabled <2. 4 v turn - off time 50% of disable to < 10% of f inal v out , v in = 0.5 v, g = +2 105 ns turn - on time 50% of disable to < 10% of f inal v out , v in = 0.5 v, g = +2 39 ns enable pin leakage current disable =+5 v 17 21 a disable pin leakage current disable = C5 v 35 44 a output characteristics output overdrive recovery time (rise/fall) v in = - 2.5 v to 2.5 v, g =+2 30/50 ns output voltage swing r l = 100 ? C 3.4 to +3.5 C 3.6 to +3.7 v r l = 1 k? C 3.7 to +3.7 C 3.8 to +3.8 v short- circuit current sinking and s ourcing 131/178 ma off isolation f = 1 mhz, disable = low C 61 db power supply operating range 5 6 v quiescent c urrent 15 16 ma quiescent current (disabled) disable = low 1.7 2 ma positive power supply rejection ratio +v s = 4 v to 6 v, Cv s = C 5 v ( i nput r eferred) 85 91 db negative power supply rejection ratio +v s = 5 v, Cv s = C 6 v to C 4 v ( i nput r eferred) 86 94 db
ad8099 data sheet rev. d | page 4 of 28 specifications with +5 v supply v s = 5 v @ t a = 25c, g = +2, r l = 1 k ? to midsupply, unless otherwise noted. refer to figure 60 through figure 66 for component values and gain configurations . table 2. parameter conditions min typ max unit dynamic performance C 3 db bandwidth g = +5, v out = 0.2 v p -p 415 440 mhz g = +5, v out = 2 v p -p 165 210 mhz bandwidth for 0.1 db flatness (soic/ lf csp) g = +2, v out = 0.2 v p -p 33/23 mhz slew rate g = +10, v out = 2 v step 630 715 v/s g = +2, v out = 2 v step 340 365 v/s settling time to 0.1% g = +2, v out = 2 v step 18 ns noise/distortion performance harmonic distortion (dbc) hd2/hd3 f c = 500 khz, v out = 1 v p - p, g = +10 C 82/ C 94 dbc f c = 10 mhz, v out = 1 v p - p, g = +10 C 80 /C 75 dbc input voltage noise f = 100 khz 0.95 nv/ hz input current noise f = 100 khz, disable pin floating 2.6 pa/ hz f = 100 khz, disable pin = +v s 5.2 pa/ hz dc performance input offset voltage 0.1 0.5 mv input offset voltage drift 2.5 v/c input bias current disable pin floating C 6.2 C 13 a disable pin = +v s C 0.2 C2 a input bias offset current 0.05 1 a input bias offset current drift 2.4 na/c open - loop gain v out = 1 v to 4 v 76 81 db input characteristics input resistance differential mode 4 k ? common mode 10 m? input capacitance 2 pf input common - mode voltage range 1.3 to 3.7 v common - mode rejection ratio v cm = 2 v to 3 v 88 105 db disable pin disable input voltage output disabled < 2.4 v turn - off time 50% of disable to <10% of final v out , v in = 0.5 v, g = +2 105 ns turn - on time 50% of disable to <10% of final v out , v in = 0.5 v, g = +2 61 ns enable pin leakage current disable = 5 v 16 21 a disable pin leakage current disable = 0 v 33 44 a output characteristics overdrive recovery time (rise/fall) v in = 0 to 2.5 v, g = +2 50/70 ns output voltage swing r l = 100 ? 1.5 to 3.5 1.2 to 3.8 v r l = 1 k? 1.2 to 3.8 1.2 to 3.8 v short- circuit current sinking and sourcing 60/80 ma off isolation f = 1 mhz, disable = low C 61 db power supply operating range 5 6 v quiescent curren t 14.5 15.4 ma quiescent current (disabled) disable = low 1.4 1.7 ma positive power supply rejection ratio +v s = 4.5 v to 5.5 v, C v s = 0 v ( i nput r eferred) 84 89 db negative power supply rejection ratio +v s =5 v, -v s = C 0.5 v to + 0. 5 v ( i nput r eferred) 84 90 db
data sheet ad8099 rev. d | page 5 of 28 absolute maximum rat ings table 3. parameter rating supply voltage 12.6 v power dissipation see figure 4 differential input voltage 1.8 v differential input current 10 ma storage temperature C 65c to +125c operating temperature range C 40c to +125c lead temperature range (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress ra t ing only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to abs o lute maximum rating conditions for extended per iods may a f fect device reliability. maximum power dissip ation the maximum safe power dissipation in the ad8099 package is limited by the associated rise in junction temperature (t j ) on the die. t he plastic encapsulating the die will locally reach the junction temperature. at approximately 150c, which is the glass transition temperature, the plastic will change its prope r ties. even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, perm a nently shifting the parametric performance of the ad8099 . exceeding a junction temperature of 1 50 c for an extended period can result in changes in sil icon devices, po tentially causing failure. the still - air thermal properties of the package and pcb ( ja ), the ambient temperature ( t a ), and the total power dissipated in the package ( p d ) determine the junction temperature of the die. the junction temperature can be calculated as ( ) ja d a j ptt += the power dissipated in the package ( p d ) is the sum of the quiescent power dissipation and the power dissipated in the pac k age due to the load drive for all outputs. the quiescent power is the voltage between the supply pins ( v s ) times the quiescent c urrent ( i s ). assuming the load ( r l ) is referenced to midsupply, the total drive power is v s /2 i out , some of which is diss i pated in the package and some in the load ( v out i out ). the difference between the total drive power and the load power is the dr ive p ower dissipated in the package. p d = quiescent power + (total drive power C load power) ( ) l 2 out l out s ss d r v C r v 2 v ivp ? ? ? ? ? ? ? ? += rms output voltages should be considered. if r l is referenced to v s C , as in single - supply operation, then the total drive power is v s i ou t . if the rms signal levels are indeterminate, consider the worst case, when v out = v s /4 for r l to midsupply: ( ) ( ) l s ss d r /v ivp 2 4 += in single - supply operation with r l referenced to v s C , worst case is v out = v s /2. airflow will increase heat dissipation, e ffectively reducing ja . also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes will reduce the ja . soldering the exposed paddle to the ground plane significantly red uces the overall thermal resista nce of the package. care must be taken to minimize parasitic capac i- tances at the input leads of high speed op amps, as di s cussed in the pcb layout section. figure 4 shows the maximum safe power d issipation in the package versus the ambient temperature for the exposed paddle (e - pad) soic - 8 ( 70 c/w), and lf csp ( 70c/w), packages on a jedec standard 4 - layer board. ja values are approximations. 04511-0-115 ambient temperature (c) 120 ?40 ?20 0 20 40 60 80 100 maximum power dissipation (watts) 0.0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 lfcsp and soic figure 4 . maximum power dissipation esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad8099 data sheet rev. d | page 6 of 28 typical performance characteristics default conditions: v s = 5 v, t a = 25c, r l = 1 k tied to ground unless otherwise noted. refer to figure 63 through figure 66 for component values and gain configurations. frequency (mhz) normalized closed-loop gain (db) 1 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 10 100 1000 04511-0-074 g = +20 g = +5 g = +2 g = +10 g = ?1 v out = 0.2v p-p v s = 5v r load = 1k ? figure 5. small signal frequency response for various gains (soic) frequency (mhz) closed-loop gain (db) 1 7 10 9 8 14 13 12 11 16 15 17 10 100 1000 04511-0-076 g = +5 v s = 5v v out = 0.2v p-p r l = 100 ? , soic r l = 1k ? , soic r l = 100 ? , csp r l = 1k ? , csp figure 6. small signal frequency response for various load resistors frequency (mhz) closed-loop gain (db) 6 5 4 3 2 1 10 9 8 7 11 1000 1 10 100 g = +2 v s = 5v r l = 1k ? +125c +85c ?40c +25c 04511-0-098 v out = 0.2v p-p figure 7. small signal frequency response for various temperatures (soic) frequency (mhz) normalized closed-loop gain (db) 1 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 10 100 1000 04511-0-073 g = +20 g = ?1 g = +2 g = +5 g = +10 v out = 0.2v p-p v s = 5v r load = 1k ? figure 8. small signal frequency response for various gains (lfcsp) frequency (mhz) closed-loop gain (db) 1 7 10 9 8 14 13 12 11 16 15 17 10 100 1000 04511-0-077 g = +5 r l = 1k ? v out = 0.2v p-p v s = 2.5v, csp v s = 2.5v, soic v s = 5v, soic v s = 5v, csp figure 9. small signal frequency response for various supply voltages frequency (mhz) closed-loop gain (db) 6 5 4 3 2 1 10 9 8 7 11 1000 1 10 100 g = +2 v s = 5v r l = 1k ? +125c +25c ?40c +85c 04511-0-097 v out = 0.2v p-p figure 10. small signal frequency response for various temperatures (lfcsp)
data sheet ad8099 rev. d | page 7 of 28 frequency (mhz) closed-loop gain (db) 1 9 10 18 19 16 14 12 17 15 13 11 20 10 100 1000 5pf, csp 5pf, soic 1pf, csp 1pf, soic 04511-0-104 g = +5 v s = 5v figure 11. small signal frequency response for various capacitive loads frequency (mhz) normalized closed-loop gain (db) 1 10 100 1000 04511-0-011 1 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 g = +2 g = +5 g = +10 g = +20 v s = 5v v out = 2v p-p r load = 1k ? figure 12. large signal frequency response for various gains (soic) 04511-0-009 frequency (mhz) closed-loop gain (db) 1 5.5 10 100 6.5 6.4 6.3 6.2 6.1 6.0 5.9 5.8 5.7 5.6 v out = 200mv p-p v out = 1.4v p-p v s = 5v g = +2 r l = 150 ? figure 13. 0.1 db flatness (soic) 04511-0-080 frequency (mhz) open-loop gain (db) open-loop phase (degrees) 0.001 0.01 0.1 1.0 10 100 1000 ?10 40 0 10 50 60 20 30 70 80 90 ?180 ?105 ?165 ?150 ?90 ?75 ?135 ?120 ?60 ?45 ?30 v s = 5v r l = 1k ? uncompensated phase magnitude figure 14. open loop frequency response frequency (mhz) normalized closed-loop gain (db) 1 10 100 1000 04511-0-012 2 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 v s = 5v v out = 2v p-p r load = 1k ? g = +5 g = +10 g = +20 g = +2 figure 15. large signal frequency response for various gains (lfcsp) 04511-0-008 frequency (mhz) closed-loop gain (db) 1 5.5 10 100 6.5 6.4 6.3 6.2 6.1 6.0 5.9 5.8 5.7 5.6 v out = 200mv p-p v out = 1.4v p-p v s = 5v g = +2 r l = 150 ? figure 16. 0.1 db flatness (lfcsp)
ad8099 data sheet rev. d | page 8 of 28 frequency (mhz) closed-loop gain (db) 1 5 8 7 6 12 11 10 9 14 13 15 10 100 1000 04511-0-078 g = +5 v s = 5v v out = 2v p-p r l = 100 ? , soic r l = 1k ? , soic r l = 100 ? , csp r l = 1k ? , csp figure 17. large signal frequency response for various load resistances frequency (mhz) input impedance (k ? ) 1 0.001 0.1 1.0 10.0 0.01 100.0 10 100 1000 04511-0-105 v s = 5v g = +2 figure 18. input impedance vs. frequency frequency (mhz) output impedance ( ? ) 0.1 0.01 1 10 100 100 0.1 1 10 1000 g = +2 g = +5 g = +10 v s = 5v 04511-0-100 figure 19. output impedance vs. frequency for various gains frequency (mhz) closed-loop gain (db) 1 5 8 7 6 12 11 10 9 14 13 15 10 100 1000 04511-0-079 g = +5 r l = 1k ? v out = 2v p-p v s = 2.5v, csp v s = 2.5v, soic v s = 5v, csp v s = 5v, soic figure 20. large signal frequency response for various supply voltages frequency (mhz) off isolation (db) 0.1 ?90 ?80 ?40 ?60 ?20 ?50 ?70 ?30 ?10 1 10 100 1000 04511-0-094 soic csp g = +2 r l = 1k ? v s = 5v v dis = 0v figure 21. off isolation vs. frequency 04511-a-008 frequency (mhz) 0.1 1.0 10.0 harmonic distortion (dbc) ?120 ?50 ?100 ?90 ?80 ?70 ?60 ?110 solid lines ? second harmonics dotted line ? third harmonics solid lines ? second harmonics dotted lines ? third harmonics g = +5 v out = 2v p-p v s = 5v r l = 100 ? soic csp figure 22. harmonic distortion vs. frequency
data sheet ad8099 rev. d | page 9 of 28 04511-a-009 frequency (mhz) 0.1 1.0 10.0 harmonic distortion (dbc) ?130 ?50 ?110 ?100 ?90 ?80 ?70 ?60 ?120 solid line ? second harmonic dotted line ? third harmonic g = +5 v out = 2v p-p v s = 5v r l = 1k ? figure 23. harmonic distortion vs. frequency (soic) 04511-a-010 frequency (mhz) 0.1 1.0 10.0 harmonic distortion (dbc) ?130 ?40 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?120 solid lines ? second harmonics dotted line ? third harmonics solid line ? second harmonic dotted line ? third harmonic g = +2 v out = 2v p-p v s = 5v r l = 1k ? figure 24. harmonic distortion vs. frequency (soic) 04511-a-011 frequency (mhz) 0.1 1.0 10.0 harmonic distortion (dbc) ?130 ?40 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?120 solid line ? second harmonic dotted line ? third harmonic g = ?1 v out = 2v p-p v s = 5v r l = 1k ? figure 25. harmonic distortion vs. frequency (soic) 04511-a-012 frequency (mhz) 0.1 1.0 10.0 harmonic distortion (dbc) ?130 ?50 ?110 ?100 ?90 ?80 ?70 ?60 ?120 solid line ? second harmonic dotted line ? third harmonic g = +5 v out = 2v p-p v s = 5v r l = 1k ? figure 26. harmonic distortion vs. frequency (lfcsp) 04511-a-013 frequency (mhz) 0.1 1.0 10.0 harmonic distortion (dbc) ?130 ?40 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?120 solid line ? second harmonic dotted line ? third harmonic g = +2 v out = 2v p-p v s = 5v r l = 1k ? figure 27. harmonic distortion vs. frequency (lfcsp) 04511-a-014 frequency (mhz) 0.1 1.0 10.0 harmonic distortion (dbc) ?130 ?40 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?120 solid line ? second harmonic dotted line ? third harmonic g = ?1 v out = 2v p-p v s = 5v r l = 1k ? figure 28. harmonic distortion vs. frequency (lfcsp)
ad8099 data sheet rev. d | page 10 of 28 04511-a-015 frequency (mhz) 0.1 1.0 10.0 harmonic distortion (dbc) ?120 ?50 ?100 ?90 ?80 ?70 ?60 ?110 solid lines ? second harmonics dotted lines ? third harmonics g = +10 r l = 1k ? v s = 2.5v v out = 1v p-p v s = 5v v out = 2v p-p figure 29. harmonic distortion vs. frequency and supply voltage (soic) 04511-a-016 output amplitude (v p-p) 7 123456 harmonic distortion (dbc) ?110 ?40 ?90 ?80 ?70 ?60 ?50 ?100 solid line ? second harmonic dotted line ? third harmonic g = +5 v s = 5v f = 10mhz r l = 100 ? figure 30. harmonic distortion vs. output amplitude (soic) 04511-a-017 output amplitude (v p-p) 7 123456 harmonic distortion (dbc) ?120 ?110 ?40 ?90 ?80 ?70 ?60 ?50 ?100 solid line ? second harmonic dotted line ? third harmonic g = +5 v s = 5v f = 10mhz r l = 1k ? figure 31. harmonic distortion vs. output amplitude (soic) 04511-a-018 frequency (mhz) 0.1 1.0 10.0 harmonic distortion (dbc) ?120 ?110 ?50 ?90 ?80 ?70 ?60 ?100 solid lines ? second harmonics dotted line ? third harmonics solid lines ? second harmonics dotted lines ? third harmonics g = +10 r l = 1k ? v s = 2.5v v out = 1v p-p v s = 5v v out = 2v p-p figure 32. harmonic distortion vs. frequency for various supplies (lfcsp) 04511-a-019 output amplitude (v p-p) 7 123456 harmonic distortion (dbc) ?110 ?40 ?90 ?80 ?70 ?60 ?50 ?100 solid line ? second harmonic dotted line ? third harmonic g = +5 v s = 5v f = 10mhz r l = 100 ? figure 33. harmonic distortion vs. output amplitude (lfcsp) 04511-a-021 output amplitude (v p-p) 7 123456 harmonic distortion (dbc) ?120 ?110 ?40 ?90 ?80 ?70 ?60 ?50 ?100 solid line ? second harmonic dotted line ? third harmonic g = +5 v s = 5v f = 10mhz r l = 1k ? figure 34. harmonic distortion vs. output amplitude (lfcsp)
data sheet ad8099 rev. d | page 11 of 28 time (ns) output voltage (v) 0510 ?0.20 ?0.05 ?0.10 ?0.15 0.15 0.10 0.05 0 0.20 15 20 25 30 35 40 45 50 1pf 10pf, 20 ? r snub 04511-0-095 r snub c l r l g = +5 v s = 5v r l = 1k ? figure 35. small signal transient response for various capacitive loads (soic) time (ns) output voltage (v) 01 0 ?0.15 ?0.05 ?0.10 0.10 0.05 0 0.15 20 30 40 50 g = +10 r l = 1k ? v s = 5.0v and 2.5v, soic v s = 5.0v and 2.5v, csp 04511-0-107 figure 36. small signal transient response for various supply voltages 04511-a-017 time (ns) 1000 0 100 200 300 400 500 600 700 800 900 output voltage (v) ?5 5 4 3 2 1 0 ?1 ?2 ?3 ?4 r l = 1k ? r l = 100 ? input 2 figure 37. output overdrive recovery for various resistive loads 04511-0-096 time (ns) output voltage (v) 0510 ?0.20 ?0.05 ?0.10 ?0.15 0.15 0.10 0.05 0 0.20 15 20 25 30 35 40 45 50 10pf, 20 ? r snub 1pf r snub c l r l g = +5 v s = 5v r l = 1k ? figure 38. small signal transient response for various capacitive loads (lfcsp) time (ns) output voltage (v) 01 0 ?0.20 ?0.05 ?0.10 ?0.15 0.15 0.10 0.05 0 0.20 20 30 40 50 r l = 1k ? , 100 ? v out = 200mv p-p g = +5 v s = 2.5v csp v s = 5.0v csp v s = 5.0v soic v s = 2.5v soic 04511-0-102 figure 39. small signal transient response for various supply voltages 04511-0-010 time (ns) output voltage (v) ?0.5 200 0 50 100 150 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 turn on turn on input turn off turn off input v s = 5v g = 2 figure 40. disable/enable switching speed
ad8099 data sheet rev. d | page 12 of 28 time (ns) output voltage (v) 01 0 ?1.5 ?0.5 ?1.0 1.0 0.5 0 1.5 20 30 40 50 g = +10 r l = 1k ? v s = 2.5v v s = 5.0v 04511-0-106 figure 41. large signal transient response vs. supply voltage (lfcsp) time (ns) output voltage (v) 01 0 ?1.5 ?0.5 ?1.0 1.0 0.5 0 1.5 20 30 40 50 v s = 5.0v g = +10 r l = 1k ? v s = 2.5v 04511-0-118 figure 42. large signal transient response vs. supply voltage (soic) time (ns) output voltage (v) 01 0 ?1.5 ?0.5 ?1.0 1.0 0.5 0 1.5 20 30 40 50 r l = 1k ? , 100 ? g = +5 v s = 5v v s = 2.5v 04511-0-101 figure 43. large signal transient response for various supply voltages and load resistances (soic and lfcsp) 04511-0-052 time (ns) output/input voltage (v) 0 5 10 15 20 25 30 35 40 ?1.5 ?0.5 ?1.0 0 0.5 1.0 1.5 ?0.3% ?0.1% ?0.2% 0% 0.1% 0.2% 0.3% 45 input error output g = +2 r load = 1k ? v s = 5v figure 44. short term settling time (lfcsp) 04511-0-051 time (ns) output/input voltage (v) 0 5 10 15 20 25 30 35 40 ?1.5 ?0.5 ?1.0 0 0.5 1.0 1.5 ?0.3% ?0.1% ?0.2% 0% 0.1% 0.2% 0.3% 45 g = +2 r load = 1k ? v s = 5v input error output figure 45. short term settling time (soic) 04511-0-050 time ( ? s) output/input voltage (v) 0 50 100 150 200 250 300 350 400 450 ?1.5 ?0.5 ?1.0 0 0.5 1.0 1.5 ?0.30% ?0.10% ?0.20% 0% 0.10% 0.20% 0.30% 500 input error output g = +2 v s = 5v figure 46. long term settling time
data sheet ad8099 rev. d | page 13 of 28 04511-0-113 frequency (mhz) 1000 0.1 1.0 10 100 common-mode rejection (db) ?110 ?20 ?30 ?50 ?70 ?40 ?60 ?80 ?90 ?100 g = +2 r l = 1k ? figure 47. common-mode rejection vs. frequency 04511-0-004 1 10 100 1k 10k 100k 1m 10m 100m 1g 1 10 100 1000 frequency (hz) input current noise (pa hz) figure 48. input current noise vs. frequency ( disable = open) 04511-0-005 1 10 100 1k 10k 100k 1m 10m 100m 1g 0.1 1 10 100 frequency (hz) input voltage noise (nv hz) figure 49. input voltage noise vs. frequency 04511-0-114 frequency (mhz) 1000 0.01 0.10 1.0 10 100 power supply rejection (db) ?100 0 ?20 ?10 ?40 ?60 ?30 ?50 ?70 ?80 ?90 g = +5 r l = 1k ? positive negative figure 50. power supply rejection vs. frequency 04511-0-003 frequency (hz) input current noise (pa hz) 1 10 100 1k 10k 100k 1m 10m 100m 1g 1 10 100 1000 figure 51. input current noise vs. frequency ( disable = +v s ) v offset ( ? v) count ?300 0 60 40 20 100 80 120 ?200 0 ?100 100 200 04511-0-075 v s = 5v n = 1,200 x = ?70 ? v ? = 80 ? v x figure 52. input offset voltage distribution
ad8099 data sheet rev. d | page 14 of 28 04511-a-003 temperature (c) 125 ?40 ?25 ?10 5 20 35 50 65 80 95 110 offset voltage ( ? v) ?200 400 200 100 300 0 ?100 v s =5v v s = 5v figure 53. input offset voltage vs. temperature 04511-a-004 temperature (c) 125 ?40 ?25 ?10 5 20 35 50 65 80 95 110 bias current ( ? a) ?6.6 ?5.4 ?5.8 ?6.0 ?5.6 ?6.2 ?6.4 i b +, v s = 5v i b +, v s =5v i b ?, v s = 5v i b ?, v s =5v figure 54. input bias current vs. temperature ( disable pin floating) 04511-a-005 temperature (c) 125 ?40?25?10?5203550658095110 output saturation voltage (v) 1.12 1.24 1.20 1.18 1.22 1.16 1.14 +v s ?v out v s =5v v s = 5v +v s ?v out ?v s +v out ?v s +v out figure 55. output saturation voltage vs. temperature 04511-a-006 temperature (c) 125 ?40 ?25 ?10 5 20 35 50 65 80 95 110 supply current (ma) 8 20 16 14 18 12 10 v s =5v v s = 5v figure 56. supply current vs. temperature 04511-a-007 temperature (c) 125 ?40 ?25 ?10 5 20 35 50 65 80 95 110 bias current ( ? a) ?1.0 1.0 ?0.2 ?0.4 0 0.2 0.4 0.6 0.8 ?0.6 ?0.8 i b +, v s =5v i b +, v s = 5v i b ?, v s =5v i b ?, v s = 5v figure 57. input bias current vs. temperature ( disable pin = +v s )
data sheet ad8099 rev. d | page 15 of 28 theory of operation the ad8099 is a voltage feedback op amp that employs a new highly linear low noise input stage. with this input stage, the ad8099 can achieve better than 90 db distortion for a 2 v p-p, 10 mhz output signal with an input referred voltage noise of less than 1 nv/ hz . this noise level and distortion performance has been previously achievable only with fully uncompensated amplifiers. the ad8099 achieves this level of performance for gains as low as +2. this new input stage also triples the achievable slew rate for comparably compensated 1 nv/ hz amplifiers. the simplified ad8099 topology is shown in figure 58. the amplifier is a single gain stage with a unity gain output buffer fabricated in analog devices extra fast complimentary bipolar process (xfcb). the ad8099 has 85 db of open-loop gain and maintains precision specifications such as cmrr, psrr, v os , and ? v os / ? t to levels that are normally associated with topologies having two or more gain stages. buffer gm c c r1 r l v out 04511-0-060 figure 58. ad8099 topology the ad8099 can be externally compensated down to a gain of 2 through the use of an rc network. above gains of 15, no exter- nal compensation network is required. to realize the full gain bandwidth product of the ad8099 , no pcb trace should be connected to or within close proximity of the external compen- sation pin for the lowest possible capacitance. external compensation allows the user to optimize the closed- loop response for minimal peaking while increasing the gain bandwidth product in higher gains, lowering distortion errors that are normally more prominent with internally compensated parts in higher gains. for a fixed gain bandwidth, wideband distortion products would normally increase by 6 db going from a closed-loop gain of 2 to 4. increasing the gain bandwidth product of the ad8099 eliminates this effect with increasing closed-loop gain. the ad8099 is available in both a soic and an lfcsp, each of which has a thermal pad for lower operating temperature. to help avoid this pad in board layout, both packages have an extra output pin on the opposite side of the package for ease in con- necting a feedback network to the inputs. the secondary output pin also isolates the interaction of any capacitive load on the output and self-inductance of the package and bond wire from the feedback loop. while using the secondary output for feed- back, inductance in the primary output will now help to isolate capacitive loads from the output impedance of the amplifier. since the soic has greater inductance in its output, the soic will drive capacitive loads better than the lfcsp. using the primary output for feedback with both packages will result in the lfcsp driving capacitive load better than the soic. the lfcsp and soic pinouts are identical, except for the rotation of all pins counterclockwise by one pin on the lfcsp. this isolates the inputs from the negative power supply pin, removing a mutually inductive coupling that is most prominent while driving heavy loads. for this reason, the lfcsp second harmonic, while driving a heavy load, is significantly better than that of the soic. a three-state input pin is provided on the ad8099 for a high impedance power-down and an optional input bias current cancellation circuit. the high impedance output allows several ad8099 s to drive the same adc or output line time inter- leaved. pulling the disable pin low activates the high impedance state. see table 5 for threshold levels. when the disable pin is left floating, the ad8099 operates normally. with the disable pin pulled within 0.7 v of the positive supply, an optional input bias current cancellation circuit is turned on, which lowers the input bias current to less than 200 na. in this mode, the user can drive the ad8099 with a high dc source impedance and still maintain minimal output referred offset without having to use impedance matching techniques. in addition, the ad8099 can be ac-coupled while setting the bias point on the input with a high dc impedance network. the input bias current cancellation circuit will double the input referred current noise, but this effect is minimal as long as wideband impedance is kept low (see figure 48 and figure 51). a pair of internally connected diodes limits the differential voltage between the noninverting input and the inverting input of the ad8099 . each set of diodes has two series diodes, which are connected in anti-parallel. this limits the differential voltage between the inputs to approximately ? 1.8 v. all of the ad8099 pins are esd protected with voltage limiting diodes connected between both rails. the protection diodes can handle 5 ma of steady state current. currents should be limited to 5 ma or less through the use of a series limiting resistor.
ad8099 data sheet rev. d | page 16 of 28 applications using the ad8099 the ad8099 offers unrivaled noise and distortion performance in low signal ga in configurations. in low gain configurations (less than15), the ad8099 requires external compensation. the amount of gain and performance needed will determine the compensation network. understanding the subtleti es of the ad8099 gives the user insight on how to exact its peak performance. use t he component values and circuit configurations shown in the applications section as starting points for designs. specific circuit applications will dictate the final configuration and value of your components. circuit components the circuit components are referenced in figure 59 , the recommended noninverting circuit schematic for the ad8099 . see table 4 for typical component values and performance data. 1 8 4 7 5 3 6 2 ad8099 c5 0.1f c c c f c1 c4 10f c2 10f c3 0.1f r c r f r g r s r1 +v s ?v s v out disable 04511-0-061 v in figure 59 . wideband noninverting gain configuration (soic) r f and r g the feedback resistor and the gain set resistor determine the noise gain of the amplifier; typical r f values range from 250 ? to 499 ?. c f creates a zero in the loop response to compensate the pole created by the input capacitance ( including stray capacitance) and the feedback resistor r f . c f helps reduce high frequency peaking and ringing in the closed - loop response. typical range is 0.5 pf to 1.5 pf for evaluation circuits used here. r1 this resistor terminates the input of the amplifier to the source resistance of the signal source, typically 50 ?. (this is application specific and not always required .) r s many high speed amplifiers in low gain configurations require that the input stage be terminated into a nominal impedance to maintain stability. the value of r s should be kept to 50 ? or lower to maintain low noise performance. at higher gains, r s may be reduced or even eliminated. typical range is 0 ? to 50 ?. c c the compensation capacitor decreases the open - loop gain at higher frequencies where the phase is degrading. by decreas - ing the open - loop gain here, the phase margin is increased and the ampli fier is stabilized. typical range is 0 pf to 5 pf. the value of c c is gain dependent. r c the series lead inductance of the package and the com - pensation capacitance (c c ) forms a series resonant circuit. r c dampens this resonance and prevents oscillations. the recommended value of r c is 50 ? for a closed - loop gain of 2. this resistor introduces a zero in the open - loop response and must be kept low so that this zero occurs at a higher frequency. the purpose of the compensation network is to decrease the open - loop gain. if the resistance becomes too large, the gain will be reduced to the resistor value , and not necessarily to 0 ?, which is what a single capacitor would do over frequency. typical value range is 0 ? to 50 ?. c1 to lower the impedance of r c , c1 is placed in parallel with r c . c1 is not required, but greatly reduces peaking at low closed - loop gains. the typical value range is 0 pf to 2 pf. c2 and c3 bypass capacitors are connected between both supplies for optimum distortion and psrr performance. these capacitors should be placed a s close a s possible to the supply pins of the amplifier. for c3, c5 , a 0508 case size should be used. the 0508 case size offers reduced inductance and better frequency response. c4 and c2 electrolytic bypass capacitors.
data sheet ad8099 rev. d | page 17 of 28 recommended values table 4. recommended values and ad8099 performance gain package feedback network values compensation network values ?3 db ss bandwidth (mhz) slew rate (v/ ? s) peaking (db) output noise ( ad8099 only) (nv/ hz ) total output noise including resistors (nv/ hz ) r f r g r s c f r c c c c1 ?1, 2 soic 250 250 50 1.5 50 4 1.5 440/700 515 0.3/3.1 2.1 4 2 lfcsp 250 250 50 0.5 50 5 2 700 475 3.2 2.1 4 ?1 lfcsp 250 250 50 1.0 50 5 2 420 475 0.8 2.1 4 5 lfcsp/soic 499 124 20 0.5 50 1 0 510 735 1.4 4.9 8.6 10 lfcsp/soic 499 54 0 0 0 0.5 0 550 1350 0.8 9.6 13.3 20 lfcsp/soic 499 26 0 0 0 0 0 160 1450 0 19 23.3 circuit configurations figure 60 through figure 66 show typical schematics for the ad8099 in various gain configurations. table 4 data was collected using the schematics shown in figure 60 through figure 66. resistor r1, as shown in figure 60 through figure 66, is the test equipment termination resistor. r1 is not required for normal operation, but is shown in the schematics for completeness. 1 8 4 7 5 3 6 2 ad8099 c5 0.1? f c c 4pf c f 1.5pf c1 1.5pf c4 10 ? f c2 10 ? f c3 0.1? f r c 50 ? r f 250 ? r g 250 ? r s 50 ? r1 50 ? +v s ?v s v out 04511-0-116 v in r l 1k ? disable figure 60. amplifier configuratio n for soic package, gain = C1 1 8 4 7 5 3 6 2 ad8099 c5 0.1? f c c 4pf c f 1.5pf c1 1.5pf c4 10 ? f c2 10 ? f c3 0.1? f r c 50 ? r f 250 ? r g 250 ? r s 50 ? r1 50 ? +v s ?v s v out 04511-0-054 v in r l 1k ? disable figure 61. amplifier configuration for soic package, gain = +2 2 1 5 8 6 4 7 3 ad8099 c5 0.1? f c c 5pf c f 1pf c1 2pf c4 10 ? f c2 10 ? f c3 0.1? f r c 50 ? r f 250 ? r s 50 ? +v s ?v s v out 04511-0-108 r g 250 ? r1 50 ? v in rl 1k ? disable figure 62. amplifier configuratio n for lfcsp package, gain =C1 2 1 5 8 6 4 7 3 ad8099 c5 0.1? f c c 5pf c f 0.5pf c1 2pf c4 10 ? f c2 10 ? f c3 0.1? f r c 50 ? r f 250 ? r g 250 ? r s 50 ? r1 50 ? +v s ?v s v out 04511-0-053 v in r l 1k ? disable figure 63. amplifier configuration for lfcsp package, gain = +2
ad8099 data sheet rev. d | page 18 of 28 fb ad8099 c5 0.1f c c 1pf c f 0.5pf c4 10f c2 10f c3 0.1f r c 50? r f 499? r g 124? r s 20? r1 50? +v s ?v s v out 04511-0-055 v in r l 1k? ? + d ?v c c v o +v disable figure 64 . amplifier configuration for l csp and soic package, gain = +5 ad8099 c5 0.1f c c 0.5pf c4 10f c2 10f c3 0.1f r f 499? r g 54? r1 50? +v s ?v s v out 04511-0-056 v in r l 1k? fb ? + d ?v c c v o +v disable figure 65 . amplifier configuration for lf csp and soic packages, gain = +10 ad8099 c5 0.1f c4 10f c2 10f c3 0.1f r f 499? r g 26? r1 50? +v s ?v s v out 04511-0-057 v in r l 1k? fb ? + d ?v c c v o +v disable figure 66 . amplifier configuration for lf csp and soic packages, gain = +20
data sheet ad8099 rev. d | page 19 of 28 performance vs. component values the influence that each component has on the ad8099 frequency response can be seen in figure 67 and figure 68. in figure 67 and figure 68, all component values are held constant, except for the individual component shown, which is varied. for example, in the r s performance plot of figure 68, all components are held constant except r s , which is varied from 0 to 50 .; and clearly indicates that r s has a major influence on peaking and bandwidth of the ad8099. 1 8 4 7 5 3 6 2 ad8099 c5 0.1? f c c c f c1 c4 10 ? f c2 10 ? f c3 0.1? f r c r f r g r s r1 +v s ?v s v ou t soic pinout shown v in disable 04511-0-117 frequency (mhz) closed-loop gain (db) ?2 3000 04511-0-020 1 10 100 1000 9 8 7 6 5 4 3 2 1 0 ?1 v s = 5v g = +2 r load = 1k ? soic package c1 = 0pf c1 = 2pf c1 = 1.5pf frequency (mhz) closed-loop gain (db) ?1 3000 04511-0-024 1 10 100 1000 10 9 8 7 6 5 4 3 2 1 0 c c = 3pf c c = 4pf c c = 5pf v s = 5v g = +2 r load = 1k ? soic package frequency (mhz) closed-loop gain (db) ?1 3000 04511-0-030 1 10 8 9 7 6 5 4 3 2 1 0 v s = 5v g = +2 r load = 1k ? soic package 10 100 1000 r c = 50 ? r c = 35 ? r c = 20 ? figure 67. frequency response for various values of c1, c c , r c
ad8099 data sheet rev. d | page 20 of 28 frequency (mhz) closed-loop gain (db) ?1 3000 04511-0-032 1 10 8 9 7 6 5 4 3 2 1 0 v s = 5v g = +2 r load = 1k ? soic package 10 100 1000 r f = r g = 200 r f = r g = 250 r f = r g = 300 frequency (mhz) closed-loop gain (db) 1 ?1 10 9 8 7 6 5 4 3 2 1 0 10 100 1000 3000 04511-0-058 c f = 1pf c f = 0.5pf c f = 1.5pf v s = 5v g = +2 r load = 1k ? soic package frequency (mhz) closed-loop gain (db) 0 10000 04511-0-034 1 12 10 11 9 8 7 6 5 4 3 2 1 v s = 5v g = +2 r load = 1k ? soic package 10 100 1000 r s = 0 r s = 50 r s = 20 1 8 4 7 5 3 6 2 ad8099 c5 0.1? f c c c f c1 c4 10 ? f c2 10 ? f c3 0.1? f r c r f r g r s r1 +v s ?v s v ou t soic pinout shown v in disable 04511-0-117 figure 68. frequency response for various values of r f , c f , r s total output noise calculations and design to analyze the noise performance of an amplifier circuit, the individual noise sources must be identified. then determine if the source has a significant contribution to overall noise perfor- mance of the amplifier. to simplify the noise calculations, we will work with noise spectral densities, rather than actual voltages to leave bandwidth out of the expressions (noise spectral density, which is generally expressed in nv/ ? hz , is equivalent to the noise in a 1 hz bandwidth). the noise model shown in figure 69 has six individual noise sources: the johnson noise of the three resistors, the op amp voltage noise, and the current noise in each input of the amplifier. each noise source has its own contribution to the noise at the output. noise is generally specified rti (referred to input), but it is often simpler to calculate the noise referred to the output (rto) and then divide by the noise gain to obtain the rti noise. all resistors have a johnson noise of ? (4kbtr) , where k is boltzmanns constant (1.38 10 C23 j/k), t is the absolute temperature in kelvin, b is the bandwidth in hz, and r is the resistance in ohms. a simple relationship, which is easy to remember, is that a 50 resistor generates a johnson noise of 1 nv ? hz at 25 ? c. the ad8099 amplifier has roughly the same equivalent noise as a 50 resistor.
data sheet ad8099 rev. d | page 21 of 28 04511-0-070 gain from "b" to output =? r2 r1 gain from "a" to output = noise gain = ng = 1 + r2 r1 i n? v n v n, r1 v n, r3 r1 r2 i n+ r3 4ktr2 4ktr1 4ktr3 v n, r2 b a v n 2 + 4ktr3 + 4ktr1 r2 2 r1 + r2 i n+ 2 r3 2 + i n? 2 r1 r2 2 + 4ktr2 r1 2 r1 + r2 r1 + r2 rti noise = rto noise = ng rti noise v out + figure 69. op amp noise analysis model in applications where noise sensitivity is critical, care must be taken not to introduce other significant noise sources to the amplifier. each resistor is a noise source. attention to the following areas is critical to maintain low noise performance: design, layout, and component selection. a summary of noise performance for the amplifier and associated resistors can be seen in table 4. input bias current and dc offset in high noise gain configurations, the effects of output offset voltage can be significant, even with low input bias currents and input offset voltages. figure 70 shows a comprehensive offset voltage model, which can be used to determine the referred to output (rto) offset voltage of the amplifier or referred to input (rti) offset voltage. 04511-0-071 gain from "b" to output =? r2 r1 gain from "a" to output = noise gain = ng = 1 + r2 r1 i b? v os r1 r2 i b+ r3 b a offset (rto) = v os 1 + r2 + i b+ r3 1 + r2 ? i b? r2 r1 r1 offset (rti) = v os + i b+ r3 ? i b? r1 r2 r1 + r2 offset (rti) = v os if i b+ = i b? and r3 = r1 r2 r1 + r2 v out for bias current cancellation: figure 70. op amp total offset voltage model for rto calculations, the input offset voltage and the voltage generated by the bias current flowing through r3 are multiplied by the noise gain of the amplifier. the voltage generated by i bC through r2 is summed together with the previous offset voltages to arrive at a final output offset voltage. the offset voltage can also be referred to the input (rti) by dividing the calculated output offset voltage by the noise gain. as seen in figure 70 if i b+ and i bC are the same and r3 equals the parallel combination of r1 and r2, then the rti offset voltage can be reduced to only v os. this is a common method used to reduce output offset voltage. keeping resistances low helps to minimize offset error voltage and keeps the voltage noise low. disable pin and input bias cancellation the ad8099 disable pin performs three functions; enable, disable, and reduction of the input bias current. when the disable pin is brought to within 0.7 v of the positive supply, the input bias current is reduced by an approximate factor of 60. however, the input current noise doubles to 5.2 pa/ ? hz . table 5 outlines the disable pin functionality. table 5. disable pin truth table supply voltage 5 v +5 v disable C5 to +2.4 0 to 2.4 enable open open low input bias current 4.3 to 5 4.3 to 5
ad8099 data sheet rev. d | page 22 of 28 8 1 4 7 5 3 6 2 ad8099 ad7667 c4 10f c c 9pf c1 2pf c5 0.1f c1 10f c2 0.1f r c 50? r f 150? r g 150? r s 50? r1 590? r2 590? +v s ?v s disable v in 04511-0-072 in refgnd ref ingnd agnd avdd dgnd dvdd dvdd c6 2.7nf r7 15? avdd 1f 47f ref 0.1f 0.1f +2.5v figure 71 . adc driver 16- bit adc driver ultralow noise and distortion p erformance make the ad8099 an ideal adc driver. even though the ad8099 is not unity gain stable, it can be configured to produce a net gain of +1 amplifier, as shown in figure 71. this is achieved by combining a gain of +2 and a gain of C 1 for a net gain of +1. the input range of the adc is 0 v to 2.5 v. table 6 shows the performance d ata of the ad8099 and the analog devices ad7667 a 1 m sps 16- bit adc. table 6 . adc driver performance, f c = 20 khz, v out = 2.2 4 v p-p parameter measurement (db) second harmonic distortion C1 11.4 third harmonic distortion C 103.2 thd C 101.4 sfdr 102.2 snr 88.1
data sheet ad8099 rev. d | page 23 of 28 circuit consideratio ns optimizing the performance of the ad8099 requires attention to detail in layout and signal routing of the board. power supply bypassing, parasitic capacitance, and component selection all contribute to the overall performance of the amplifier. the ad8099 features an expos ed paddle on the backs of both the lf csp and soic packages. the exposed paddle provides a low thermal resistive path to the ground plane. for best performance, solder the exposed paddle to the ground plane. pcb layout the compensation network is determined by the amplifier gain requirements . for lower gains, the layout and component placement are more critical. for higher gains , there are fewer compensation components, which results in a less complex layout. with diligent consideration to layout, grounding, and component placement, the ad8099 evaluation boards have been optimized for peak performance. these are the same evaluation boards that are av ailable to customers ; see the ordering guide for ordering information. parasitics the area surrounding the compensation pin is very sensitive to parasitic capacitance. to realize the full gain bandwidth product of the ad8099 , there should be no trace connected to or within close proximity of the external compensation pin for the lowest possible capacitance. when compensation is required, the traces to the compensation pi n, the ne gative supply, and the intercon nect between components (i.e. c c , c1, and r c in figure 59) should be made as wide as possible to minimize inductance. all ground and power planes under the pins of the ad8099 should be cleared of copper to prevent parasitic capacitance between the input and output pins to ground. a single mount - ing pad on a soic footprint can add as much as 0.2 pf of capacitance to ground as a result of not clearing the ground or power plane under the ad8099 pins. parasitic capacitance can cause peaking and instability, and should be minimized to ensure proper operation. the new pinout of the ad8099 reduces the distance between the output and the inverting input of the amplifier. this helps to minimize the parasitic inducta nce and capacitance of the feedback path, which, in turn, reduce s ringing and second harmonic distortion. grounding when possible, ground and power planes should be used. ground and power planes reduce the resistance and inductance of the power supply fee ds and ground returns. if multiple planes are used , they should be stitched together with multiple vias. the returns for the input, output terminations, bypass capacitors , and r g should all be kept as close to the ad8099 as possible. ground vias should be placed at the very end of the component mounting pad to provide a solid ground return. the output load ground and the bypass capacitor grounds should be returned to a common point on the ground plane to minimize parasitic inductance and improve distortion performance. the ad8099 packages feature an exposed paddle. for optimum performance, solder this paddle to ground. for more infor - ma tion on pcb layout and design considerations , refer to section 7 - 2 of the 2002 analog devices op amp applications book. power supply bypassing the ad8099 power supply bypassing has been optimize d for each gain configuration as shown in figure 60 through figure 66 in the circuit configurations section. the values shown should be used when possible. bypassing is critical for stability, frequency response, distortion, and psrr performance. the 0.1 f capacitors shown in figure 60 through figure 66 should be as close to the supply pins of the ad8099 as possible and the electrolytic capacitors b eside them. component selection smaller components less than 1206 smt case size, offer smaller mounting pads, which have less parasitics and allow for a more compact layout. it is critical for optimum performance that high quality, tight tolerance (where critical) , and low drift compo - nents be used. for example, tight tolerance and low drift is critical in the selection of the feedback capacitor used in figure 60 . the feedback compensation capacitor in figure 60 is 1.5pf. this capacitor should be specified with npo material. npo material typically has a 30 ppm/ c change over C 55c to + 125 c temperature range. for a 100 c chan ge, this would result in a 4.5 ff change in capacitance, compared to an x7r material, which would result in a 0.23 pf change, a 15% change from the nominal value. this could introduce excessive peaking , as shown in figure 68 , c f v s. frequency r esponse. design tools and tec hnical support analog devices is committed to the design process by providing technical support and online design tools. adi offers technical support via evaluation boards, sample ics, spice models, interactive ev aluation tools, application notes, phone and email support all available at www.analog.com .
ad8099 data sheet rev. d | page 24 of 28 outline dimensions compliant to jedec standards ms-012-a a 06-02-2011-b 1.27 0.40 1.75 1.35 2.29 2.29 0.356 0.457 4.00 3.90 3.80 6.20 6.00 5.80 5.00 4.90 4.80 0.10 max 0.05 nom 3.81 ref 0.25 0.17 8 0 0.50 0.25 45 coplanarity 0.10 1.04 ref 8 1 4 5 1.27 bsc s eating plane for proper connection of the exposed pad, refer to the connection diagrams section of this data sheet. bottom view top view 0.51 0.31 1.65 1.25 figure 72. 8-lead standard small outline package, with exposed pad [soic_n_ep] narrow body (rd-8-1) dimensions shown in millimeters 1 exposed pa d (bottom view) 0.50 bsc pin 1 indicator 0.50 0.40 0.30 top view 12 max 0.70 max 0.65 typ 0.90 max 0.85 nom 0.05 max 0.01 nom 0.20 ref 1.89 1.74 1.59 4 1.60 1.45 1.30 3.25 3.00 sq 2.75 2.95 2.75 sq 2.55 5 8 pin 1 indicator seating plane 0.30 0.23 0.18 0.60 max 0.60 max 04-04-2012-a for proper connection of the exposed pad, refer to the connection diagrams section of this data sheet. figure 73. 8-lead lead frame chip scale package [lfcsp_vd] 3 mm 3 mm body, very thin, dual lead (cp-8-2) dimensions shown in millimeters
data sheet ad8099 r ev. d | page 25 of 28 ordering guide model 1 or dering quantity temperature range package description branding package option ad8099 ard 98 C 40c to +125c 8- lead soic_n_ep rd -8-1 ad8099 ard - reel 2,500 C 40c to +125c 8- lead soic_n_ep rd -8-1 ad8099 ard - reel7 1,000 C 40c to +125c 8- lead soic_n_ep rd -8-1 ad8099 ardz 98 C 40c to +125c 8 - lead soic_n_ep rd - 8 - 1 ad8099 ardz - reel 2,500 C 40c to +125c 8- lead soic_n_ep rd -8-1 ad8099 ardz - reel7 1,000 C 40c to +125c 8- lead soic_n_ep rd -8-1 ad8099 acpz - r2 250 C 40c to +125c 8- lead lead frame chip scale package [lfcsp_vd] hdb cp -8-2 ad8099 acpz - reel 5,000 C 40c to +125c 8- lead lead frame chip scale package [lfcsp_vd] hdb cp -8-2 ad8099 acpz - ree l7 1,500 C 40c to +125c 8 - lead lead frame chip scale package [lfcsp_vd] hdb cp - 8 - 2 ad8099 acpi - ebz evaluation board for inverting 8- lead lfcsp_vd ad8099 acpn - ebz evaluation board for noninverting 8- lead lfcsp_vd ad8099 ardi - ebz evaluation board for inverting 8- lead soic_n_ep ad8099 ardn - ebz evaluation board for noninverting 8- lead soic_n_ep 1 z = rohs compliant part.
ad8099 data sheet r ev. d | page 26 of 28 notes
data sheet ad8099 r ev. d | page 27 of 28 notes
ad8099 data sheet r ev. d | page 28 of 28 notes ? 200 3C 2013 analog devices, inc. all rights reserved. trademarks and regi s tered trademarks are the property of their respective owners. d 04511 C0C 8 / 1 3( d )

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